We are seeking highly motivated and experienced who can lead and build a team to perform design implementation (PnR) and required signoff verifications of full chip and/or digital blocks using ASIC design flow (Gate2GDSII or RTL2GDSII).

Job Description

• Hands-on and rich experience of implementing (PnR) complex full chip/SOC and digital blocks using Synopsys state of the art Gate to GDSII ASIC design flows mainly including Design Initialization, IO and bump placement, RDL routing, Power planning, Floor planning/Macro placement, Scan-chain reordering, CTS, Route and chip finishing steps
• Perform design partitioning to enable hierarchical design flow implementation
• Perform bump placement and RDL routing working closely with package substrate design team to achieve package signoff closure and meeting reliability (EMIR and SI/PI) targets
• Perform Physical Implementation of full chip and digital blocks starting from gate netlist till gds out
• Perform signoff verifications including Layout verifications (DRC, LVS, Antenna) and Reliability verifications (EMIR, ESD) of the full chip along with the digital blocks
• Ownership of writing MCMM and UPF for the full chip and digital block designs
• Work with Synthesis team to provide feedback on SDC for alignment/cleanup as required
• Provide handoff data to enable signoff closures like STA, Formality, Layout and Reliability verification
• To work closely with signoff teams to ensure timely closure of all signoff stages
• To adapt and maintain design flows required for automated execution of state-of-the-art implementation of full chip and digital blocks
• Provide regular status of design implementation using KPI at each stage of the flow indicating completion and signoff

Job Requirements

• Excellent understanding of Digital design architectures and synchronous high speed interfaces including concepts of FIFO, PHY and Redundancy
• JTAG and APB interface implementation experience is a must
• Expertise and in-depth understanding of the ASIC Physical design flow steps of starting from Gate netlist for full chip
• Excellent Understanding of IP library CAD data and views (lef, liberty, Verilog,
• Experience in Synthesis flow and DFT insertion with Fusion Compiler is a definite plus
• Experience in implementing Boundary scan (BSDL) is desirable
• Experience in working on IO integration with Wire-bond or Flip-chip design is a must
• Exposure to Synopsys Tool set (such as FC/ICC2, Primetime, Formality, ICV) is a must including Ansys Redhawk
• Hands-on experience in writing automations using scripting languages like tcl, python and perl is a must
• Exposure to leading foundries such as TSMC, Intel, Samsung and GF FinFET technologies and designs is desirable
• Experience in Testchip implementation and ATE/Bench testing exposure is a plus

Experience : 15+ years of Relevant experience in Physical design domain and Tapeouts

Education : B.E/B.Tech/M.Tech in ECE/EE